1. Field of the Invention
The present invention relates to a variable length code decoder which outputs from a variable length code having a variable length code part and a sign bit for indicating the sign of the code a fixed length code associated with the code part and the sign bit.
2. Description of the Prior Art
A variable length code increases its coding efficiency by assigning a short code to an event that has a high probability of occurrence and reduces the average code length. Hence, variable length codes are widely used to codify pictures that need to be coded with a high efficiency. As examples of coding systems which perform variable length coding, MPEG (Moving Picture Expert group) and H.261 and the like are currently used widely for systems which record or transmit moving pictures.
Decoders which reproduce moving pictures coded by such coding systems are installed in various AV products. It is desirable that the costs and power consumption of these products be low. Therefore, it is desirable that the structures and constitutive components of such decoders be simplified.
FIG. 1 shows the configuration of a conventional decoder 100. FIG. 2 shows variable length codes that the decoder 100 shown in FIG. 1 processes.
The decoder 100 shown in FIG. 1 has a code buffer 1 to which the variable length codes VLC shown in FIG. 2 are input, a shift unit 2 to which the variable length codes VLC are supplied serially via the code buffer 1, and a control unit 3 which controls the code buffer 1 and shift unit 2.
Each of the variable length codes VLC shown in FIG. 2 has a numerical part and a 1-bit sign part. The numerical part has been codified in accordance with the absolute value of the data, forming a variable length code. The sign part represents the sign of the data and is provided after the numerical part.
A decoding unit 10 having a numerical part decoding unit 41, a sign decoding unit 12, and a code length decoding unit are connected to the shift unit 2. The numerical part decoding unit 41 receives 5-bit code information C0, C1, C2, C3, and C4 from the shift unit 2, decodes the significant numerical part of this code information, and outputs binary numerical data D0 and D1. The numerical part decoding unit 41 is constructed by combining inverters 41a, 41b, and 41c, logic product gates 41d, 41e, 41f, and 41g (hereafter, these logic product gates will be referred to as AND), and logic sum gates 41h and 41i (hereafter, these logic sum gates will be referred to as OR).
The sign decoding unit 12 decodes the sign of the code information C0 through C4 supplied from the shift unit 2 and outputs sign data S. The sign decoding unit 12 is constructed by combining AND logic gates 12a, 12b, and 12c with an OR logic gate 12d. The code length decoding unit 42 decodes the number of bits that constitute one variable length code VLC based on the code information C0 through C4 supplied from the shift unit 2, and outputs a code length information CL. Like the data decoding unit 41 and sign decoding unit 12, the code length decoding unit 42 is constructed by combining several logic gates.
The output terminal of the code length decoding unit 42 is connected to the control unit 3. The control unit 3 sequentially supplies variable length codes VLC to the code buffer 1 based on the code length information CL to have the code buffer 1 read in the variable length codes VLC. In addition, the control unit 3 controls the shift unit 2 so as to make the shift unit 2 shift the received information by a prescribed number of bits. The 5-bit code information C0 through C4 is then supplied to the decoding unit 10.
Next, the operation will be explained in which the variable length codes VLC corresponding to the data "+1", "-3", and "-2" others are sequentially input to the code buffer 1 in this order. As shown in FIG. 2, the variable length codes VLC that correspond to the data "+1", "-3", and "-2" are "010", "00011", and "0011", respectively. Hence, these data are combined to produce a code "010000110011" and a subsequent variable length code (for example, 00011 . . . ) which are stored in the code buffer 1. The code "010000110011" stored in the code buffer 1 is then supplied serially to the shift unit 2. The first five bits 01000 of the code "010000110011" supplied to the shift unit 2 is then sent as code information C0 through C4 to the decoding unit 10.
The numerical part decoding unit 41 of the decoding unit 10 decodes the numerical part of the data "+1", and outputs "1" and "0" as numerical data D0 and D1, respectively. Meanwhile, the sign decoding unit 12 decodes the sign of the data "+1", and outputs "0" as sign data S. In addition, the code length decoding unit 42 decodes the code length of the data "+1", and outputs "3" as a code length information CL.
The code length information CL (=3) obtained by decoding the data "+1" is supplied to the control unit 3. The control unit 3 then controls the shift unit 2 so that the shift unit 2 will shift the variable length code VLC "010000110011" inside the shift unit 2 by three bits to the left. The first five bits of the post-shift variable length code VLC are "00011". These five bits are then supplied as code information C0 through C4 to the decoding unit 10. In other words, this code information C0 through C4 is the variable length code VLC of the second data "-3". Therefore, the decoding unit 10 decodes the data "-3", and outputs "1" and "1" as numerical data D0 and D1, respectively, "1" as sign data S, and "5" as a code length information CL.
The code length information CL (=5) obtained by decoding the data "-3" is supplied to the control unit 3. The control unit 3 then controls the shift unit 2 so that the shift unit 2 will shift the variable length code VLC inside the shift unit 2 by five bits to the left. The first five bits of the post-shift variable length code VLC are "00110". These five bits are then supplied as code information C0 through C4 to the decoding unit 10. In other words, this code information CO through C4 is the variable length code VLC of the third data "-2". Therefore, the decoding unit 10 decodes the data "-2", and outputs "0" and "1" as numerical data D0 and D1, respectively, "1" as sign data S, and "4" as a code length information CL.
The above-described process is repeated to sequentially decode the variable length codes VLC input to the code buffer 1.
However, according to the above-described conventional decoder, as the number of variable length codes increases, the circuit size of the decoding unit must be increased, which is a problem.
For example, a valiable length code coded by the MPEG (Moving Picture Expert Group) system that is used to code moving pictures has several hundred codes. Therefore, the circuit size of the variable length code decoding unit has to be increased, which results in an increased amount of power consumption.
Given these circumstances, it is an object of the present invention to provide variable length code decoders having a simple circuit structure. It is also an object of the present invention to provide moving picture decoders in which such variable length code decoders are used.